Eur. Phys. J. Appl. Phys.
Volume 66, Number 2, May 2014
|Number of page(s)||7|
|Section||Semiconductors and Devices|
|Published online||05 June 2014|
Measurement and numerical analysis of C-V characteristics for normally-on SiCED-JFET
University of Monastir, Micro-electronics and Instrumentation Laboratory, Environment Boulevard, 5019
2 Institut National des Sciences Appliquées de Lyon (INSA-Lyon), Laboratoire Ampére, UMR 5005, 69621 Villeurbanne, France
a e-mail: firstname.lastname@example.org
Revised: 11 March 2014
Accepted: 17 April 2014
Published online: 5 June 2014
In this paper, terminal capacitances of a normally-on SiCED-JFET are measured, analyzed and simulated. All these capacitances are measured using an auto-balanced (guarded) capacitance test-bench that leads to the standard 3-terminal model capacitors CGS, CDS and CGD. This test bench is developed to measure each capacitance individually, without any mutual influence. 2D finite-element simulations are used to show that the capacitance CGD cannot be modeled by a standard planar junction model. This is due to the influence of two dimensional effects around the buried layer P+. A new analytical model of CGD is proposed. A good agreement is obtained between simulations and measurements of the different capacitances.
© EDP Sciences, 2014
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