Measurement and numerical analysis of C-V characteristics for normally-on SiCED-JFET

¹ University of Monastir, Micro-electronics and Instrumentation Laboratory, Environment Boulevard, 5019 Monastir, Tunisia
² Institut National des Sciences Appliquées de Lyon (INSA-Lyon), Laboratoire Ampére, UMR 5005, 69621 Villeurbanne, France

^a e-mail: ghedirasam@yahoo.fr

Received: 22 November 2013
Revised: 11 March 2014
Accepted: 17 April 2014
Published online: 5 June 2014

Abstract

In this paper, terminal capacitances of a normally-on SiCED-JFET are measured, analyzed and simulated. All these capacitances are measured using an auto-balanced (guarded) capacitance test-bench that leads to the standard 3-terminal model capacitors C_GS, C_DS and C_GD. This test bench is developed to measure each capacitance individually, without any mutual influence. 2D finite-element simulations are used to show that the capacitance C_GD cannot be modeled by a standard planar junction model. This is due to the influence of two dimensional effects around the buried layer P⁺. A new analytical model of C_GD is proposed. A good agreement is obtained between simulations and measurements of the different capacitances.