| Issue |
Eur. Phys. J. AP
Volume 5, Number 2, February 1999
|
|
|---|---|---|
| Page(s) | 171 - 178 | |
| DOI | https://doi.org/10.1051/epjap:1999126 | |
| Published online | 15 February 1999 | |
https://doi.org/10.1051/epjap:1999126
PSPICE model of the power LDMOS transistor for radio frequency applications in the 1.8 – 2.2 GHz Band
1
École supérieure de technologie, Complexe universitaire, B.P. 473, Oujda,
Marocco
2
Laboratoire d'Électronique Appliquée et d'Automatique (LEAA),
Route sidi Maâfa, B.P.
524, Oujda, Marocco
3
Laboratoire d'Analyse et d'Architecture des Systèmes (LAAS), 7 avenue du Colonel Roche
31077 Toulouse, France
4
RF Semiconductor
Division, Motorola Semiconducteurs S.A., B.P. 1029, 31023 Toulouse Cedex, France
Received:
24
June
1998
Accepted:
6
November
1998
Published online: 15 February 1999
In this paper, we propose a model for the LDMOS transistor used for power amplification in the frequencies band 1.8–2.2 GHz dedicated to the mobile telephony system Digital Cellular System (DCS). This model takes into account the behaviour of each internal region of the power structure. A new representation of the non-linear inter-electrode capacitances, drain-gate Cgd and drain-source Cds, is proposed. The obtained model is implemented in the circuit simulator PSPICE, which gives an overall evaluation of the transistor performances in the radio frequency power amplification mode. This model is Maynly intended to the system designer. A study of the power amplification in the SHF band at 2 GHz is performed. A good agreement between experimental and simulation results is found.
PACS: 73.40.Qv – Metal-insulator-semiconductor structures (including semiconductor-to-insulator)
© EDP Sciences, 1999
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