Regular Article

Hole trapping capability of silicon carbonitride charge trap layers^★

Graduate School of Engineering, Tokai University, 4-1-1 Kitakaname, Hiratsuka, Kanagawa 259-1292, Japan

^* e-mail: kkbys@keyaki.cc.u-tokai.ac.jp

Received: 28 September 2019
Received in final form: 10 December 2019
Accepted: 2 June 2020
Published online: 14 July 2020

Abstract

We have evaluated the hole trapping capability of the silicon carbonitride (SiCN) dielectric film for application in metal-oxide-nitride-oxide-silicon (MONOS)-type non-volatile memory devices. After a great number of holes were injected to the SiCN charge trap layer of memory capacitors at high applied voltages, the flat-band voltage shift ΔV _fb,h of the capacitors was saturated and the charge centroid location of holes trapped in the SiCN layer was found to reach at 1.8–2.0 nm from the blocking oxide-charge trap layer interface. Using the obtained ΔV _fb,h and charge centroid values, the maximum density of holes trapped in the SiCN layer was estimated to be 1.2 × 10¹³ holes/cm², which was higher than that trapped in a silicon nitride charge trap layer (=1.0 × 10¹³ holes/cm²). It is concluded that the high density of trapped holes caused large ΔV _fb,h in the memory capacitors with the SiCN layer.