Regular Article

Effect of strain in silicon nanotube FET devices for low power applications

¹ Department of Electrical Engineering, NIT, Silchar, India
² Electronics and Telecommunication Engineering Department, Jadavpur University, Kolkata, India

^* e-mail: avtar.ju@gmail.com

Received: 7 August 2018
Received in final form: 26 October 2018
Accepted: 20 December 2018
Published online: 6 February 2019

Abstract

In this paper, we have presented an analysis on the performance of a strained silicon channel in silicon nanotube FET (Si-NTFET) device. Si-NTFET devices have tube-shaped channel region and because of this conduction in the channel can be controlled in two ways from outside the tube and from inside (from hollow side) the tube which results in better control over the short channel effects (SCEs). Bi-axial strain induced into the device by the inclusion of silicon-–germanium layer in between the channel. Three-dimensional simulations of the structure are carried out using ATLAS TCAD simulator and the model is calibrated with respect to previously published experimental data. The transfer characteristics, drain induced barrier lowering (DIBL), threshold voltage, I_on and I_off, subthreshold swing of the Si-NTFET and strained Si-NTFET devices are investigated. It is seen that in strained Si-NTFET, the drive capability and inversion charge density is much higher compared to that of Si-NTFET. Evaluation of electrical performances confirms that the DIBL and other SCEs are either reduced or remains the same. However, the use of strained Si-NTFET is more suited for high speed and low power applications.