| Issue |
Eur. Phys. J. Appl. Phys.
Volume 42, Number 2, May 2008
|
|
|---|---|---|
| Page(s) | 87 - 94 | |
| Section | Microelectronics and Optoelectronics | |
| DOI | https://doi.org/10.1051/epjap:2008047 | |
| Published online | 29 April 2008 | |
https://doi.org/10.1051/epjap:2008047
An analytical study of hot-carrier degradation effects in sub-micron MOS devices
Senior Lecturer Faculty of Engineering and Technology
Multimedia University, Melaka Campus, Melaka, Malaysia
Corresponding author: aks_1993@yahoo.co.uk
Received:
25
September
2007
Revised:
12
December
2007
Accepted:
31
January
2008
Published online:
29
April
2008
In this present communication, we have studied the effect of hot-carrier degradation effects on surface potential, threshold voltage and DIBL of the sub-micron device. We have derived a more accurate model for the threshold voltage in the presence of hot carrier degradation effect. Our model includes a fitting parameter to take care of short channel effects. The validity of our model is verified by the MINIMOS simulator results. Our analysis predicts that the minimum potential position along the channel is not affected by the sign of the hot carrier induced localized interface charge density and always occurs in damage free region. DIBL effect is more pronounced in submicron devices in the presence of the hot carrier degradation effect.
PACS: 81.05.Hd – Other semiconductors
© EDP Sciences, 2008
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