Design and characterization of high voltage devices integrated in a standard CMOS technology

¹ Atmel ES2, 13500 Rousset, France
² Centre de Génie Électrique de Lyon, Institut National des Sciences Appliquées de Lyon, 20 avenue A. Einstein, 69621 Villeurbanne Cedex, France

Corresponding author: gontrand-@cegely.insa-lyon.fr

Received: 5 June 2000
Revised: 30 March 2001
Accepted: 29 June 2001
Published online: 15 November 2001

Abstract

A fully silicon CMOS compatible high voltage (H-V) integrated circuit has been developed that features 5-V high performance digital CMOS with H-V devices. The high voltage device has to support voltage drop upper 50 V between drain and source, both for NMOS and PMOS transistors. It will be placed only in the input and output circuit, for interface application. A lateral diffusion MOS (LDMOS) structure has been chosen, for its compatibility with 5 V CMOS devices. Two specific implants are introduced into the standard process. They create the high voltage N and P junctions. Numerical simulations are performed to determine specific implant characteristics. Moreover, a two-dimensional simulator gives best LDMOS dimensions. A process control monitor has been done according to these results. After the technological realization, a quantitative electrical characterization, as maximal breakdown voltage, determines the best architecture. These devices are modeled by the MOS SPICE2G Level3, which gives sufficient results for digital applications. A simple circuit, a 5 V-50 V buffer, is simulated, realized and characterized, to conclude this work.