Eur. Phys. J. Appl. Phys.
Volume 57, Number 1, January 2012
|Number of page(s)||12|
|Section||Semiconductors and Devices|
|Published online||02 December 2011|
Design of complementary LDMOS in 0.35 μm BiCMOS technology for smart integration
Université de Lyon, Institut des Nanotechnologies de Lyon INL-UMR5270, CNRS, INSA de Lyon, 69621 Villeurbanne Cedex, France
2 Faculty of Engineering, Ain Shams University, Cairo, Egypt
a e-mail: firstname.lastname@example.org
Revised: 24 January 2011
Accepted: 25 August 2011
Published online: 2 December 2011
In this paper, an nLDMOS and a pLDMOS are developed by slight modifications of the base process steps of 0.35 μm BiCMOS technology. Extra two masks are used for the formation of the body region and the drift region with slightly added thermal budget and without resorting to high-tilt implants. The specific ON-resistance (RON,SP) and the OFF-state breakdown voltage (BV) are 1.5 mΩ cm2 and 60 V, for the nLDMOS and 3.0 mΩ cm2 and 160 V, for the pLDMOS, so the devices can typically be operated around 42 V supply voltage, which is suitable for the new automotive applications. An isolation mechanism between the power devices is suggested using a deep trench filled with silicon dioxide and undoped polysilicon. The polysilicon has a nearly perfect conformal deposition, that is, both step coverage and bottom coverage are 100%. A simple subcircuit model is built using a two module approach, one for the intrinsic MOS area and the other for the drift region. The Spice model parameters of the intrinsic MOS part are extracted using a system that links the ICCAP extraction tool with the results of the ISE-TCAD tools. The simulation results using the Spice model are compared to the results provided by ISE-TCAD tools, and the accuracy at room temperature is less than 5% for the whole voltage domain. An interface circuit, to convert 0/3.3 V to 0/42 V, suitable for automotive applications, is proposed.
© EDP Sciences, 2011
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