Neural harmonic detection approaches for FPGA area efficient implementation

¹ Institut d’Électronique du Solide et des Systèmes (InESS), Université de Strasbourg/CNRS, UMR 7163, 23 rue du Lœss, 67037 Strasbourg Cedex, France http://www-iness.c-strasbourg.Fr
² Laboratoire d’Électronique, Électrotechnique, Automatique et Télécommunication (LEEAT), Université de Douala, B.P. 8698 Douala, Cameroun
³ Institut National Supérieur des Sciences Appliquées de Strasbourg, Laboratoire GREEN (UMR 7037, CNRS) Antenne de Strasbourg, 24 Bd de la Victoire, 67084 Strasbourg Cedex, France
⁴ École Nationale Supérieure Polytechnique, Université de Yaoundé I, BP 8390 Yaoundé, Cameroun

^a e-mail: serge.dzonde@iness.c-strasbourg.Fr

Received: 27 August 2010
Revised: 7 January 2011
Accepted: 25 July 2011
Published online: 14 November 2011

Abstract

This paper deals with new neural networks based harmonics detection approaches to minimize hardware resources needed for FPGA implementation. A simple type of neural network called Adaline is used to build an intelligent Active Power Filter control unit for harmonics current elimination and reactive power compensation. For this purpose, two different approaches called Improved Three-Monophase (ITM) and Two-Phase Flow (TPF) methods are proposed. The ITM method corresponds to a simplified structure of the three-monophase method whereas the TPF method derives from the Synchronous Reference Frame method. Indeed, for both proposed methods, only 50% of Adalines with regard to the original methods is used. The corresponding designs were implemented on a FPGA Stratix II platform through Altera DSP Builder^® development tool. After analyzing those two methods with respect to performance and size criteria, a comparative study with the popular p-q and also the direct method is reported. From there, one can notice that the p-q is still the most powerful method for three-phase compensation but the TPF method is the fastest and the most compact in terms of size. An experimental result is shown to validate the feasibility of FPGA implementation of ANN-based harmonics extraction algorithms.