Eur. Phys. J. Appl. Phys.
Volume 27, Number 1-3, July-September 2004Tenth International Conference on Defects: Recognition, Imaging and Physics in Semiconductors (DRIP X)
|Page(s)||479 - 482|
|Section||Electronic properties through contactless characterisation|
|Published online||15 July 2004|
Microscopic C-V measurements of SOI wafers by scanning capacitance microscopy
Department of Electrical Engineering and Computer
Sciences, Graduate School of Engineering, Himeji
Institute of Technology, 2167 Shosha, Himeji
Corresponding author: firstname.lastname@example.org
Accepted: 2 October 2003
Published online: 15 July 2004
Scanning capacitance microscopy (SCM) has been applied to microscopic characterization of electrical properties of silicon-on-insulator (SOI) wafers. Two kinds of capacitance-voltage (C-V) methods have been proposed for separately characterizing the electrical properties of a gate oxide, an SOI layer, a buried oxide (BOX) layer, a Si substrate, and their interfaces: (i) a front-gate C-V method whereby the electrical properties of the gate oxide and front SOI (the gate oxide/SOI) interface can be characterized, and (ii) a back-gate C-V method for the characterization of the electrical properties of the BOX layer, back SOI (the BOX/SOI) interface, and the BOX/Si substrate interface. Furthermore, SCM images of the sampled SOI wafer have been obtained for visualizing the microscopic spatial distribution of electrical properties of SOI wafers by using the proposed C-V methods. These SCM images revealed the fluctuation in the oxide charges and interface traps. SCM has been demonstrated to be an effective tool for microscopic electrical characterization of SOI wafers.
PACS: 07.79.-v – Scanning probe microscopes and components / 68.37.-d – Microscopy of surface, interfaces, and thin films / 81.70.-q – Methods of materials testing and analysis / 85.30.-z – Semiconductor devices
© EDP Sciences, 2004
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