Microscopic C-V measurements of SOI wafers by scanning capacitance microscopy

Department of Electrical Engineering and Computer Sciences, Graduate School of Engineering, Himeji Institute of Technology, 2167 Shosha, Himeji 671-2201, Japan

Corresponding author: yoshida@eng.u.hyogo.ac.jp

Received: 4 July 2003
Accepted: 2 October 2003
Published online: 15 July 2004

Abstract

Scanning capacitance microscopy (SCM) has been applied to microscopic characterization of electrical properties of silicon-on-insulator (SOI) wafers. Two kinds of capacitance-voltage (C-V) methods have been proposed for separately characterizing the electrical properties of a gate oxide, an SOI layer, a buried oxide (BOX) layer, a Si substrate, and their interfaces: (i) a front-gate C-V method whereby the electrical properties of the gate oxide and front SOI (the gate oxide/SOI) interface can be characterized, and (ii) a back-gate C-V method for the characterization of the electrical properties of the BOX layer, back SOI (the BOX/SOI) interface, and the BOX/Si substrate interface. Furthermore, SCM images of the sampled SOI wafer have been obtained for visualizing the microscopic spatial distribution of electrical properties of SOI wafers by using the proposed C-V methods. These SCM images revealed the fluctuation in the oxide charges and interface traps. SCM has been demonstrated to be an effective tool for microscopic electrical characterization of SOI wafers.