Eur. Phys. J. Appl. Phys.
Volume 63, Number 1, July 2013
International Semiconductor Conference Dresden-Grenoble – ISCDG 2012
|Number of page(s)||12|
|Published online||05 July 2013|
Energy efficiency enhancements for semiconductors, communications, sensors and software achieved in cool silicon cluster project*
Technische Universität Dresden, Helmholzstrasse 18, 1069 Dresden, Germany
2 NaMLab, Nöthnitzer Straße 64, 01187 Dresden, Germany
3 Fraunhofer, Technologie-Campus 3, 09126 Chemnitz, Germany ; Maria-Reiche-Straße 2, 01109 Dresden
4 Globalfoundries, Wilschdorfer Landstraße 101, 01109 Dresden, Germany
5 Infineon, Königsbrücker Straße 180, 01099 Dresden, Germany
6 Silicon Saxony, Manfred-von-Ardenne-Ring 20, 01099 Dresden, Germany
7 Radioopt, Altmarkt 10, 01067 Dresden, Germany
8 Plastic Logic, An der Bartlake 5, 01109 Dresden, Germany
9 Roth&Rau, An der Baumschule 6-8, 09337 Hohenstein-Ernstthal, Germany
10 nxp, Am Waldschlösschen 1, 01099 Dresden, Germany
11 xfab, Grenzstrasse 28, 01109 Dresden, Germany
12 Productivity Engineering, Sachsenallee 9, 01723 Kesselsdorf, Germany
a e-mail: Frank.Ellinger@tu-dresden.de
Accepted: 9 April 2013
Published online: 5 July 2013
An overview about the German cluster project Cool Silicon aiming at increasing the energy efficiency for semiconductors, communications, sensors and software is presented. Examples for achievements are: 1000 times reduced gate leakage in transistors using high-fc (HKMG) materials compared to conventional poly-gate (SiON) devices at the same technology node; 700 V transistors integrated in standard 0.35 μm CMOS; solar cell efficiencies above 19% at < 200 W/m2 irradiation; 0.99 power factor, 87% efficiency and 0.088 distortion factor for dc supplies; 1 ns synchronization resolution via Ethernet; database accelerators allowing 85% energy savings for servers; adaptive software yielding energy reduction of 73% for e-Commerce applications; processors and corresponding data links with 40% and 70% energy savings, respectively, by adaption of clock frequency and supply voltage in less than 20 ns; clock generator chip with tunable frequency from 83-666 MHz and 0.62-1.6 mW dc power; 90 Gb/s on-chip link over 6 mm and efficiency of 174 fJ/mm; dynamic biasing system doubling efficiency in power amplifiers; 60 GHz BiCMOS frontends with dc power to bandwidth ratio of 0.17 mW/MHz; driver assistance systems reducing energy consumption by 10% in cars
© EDP Sciences, 2013
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