Delay modeling of high-speed distributed interconnect for the signal integrity prediction

IRSEEM (Research Institute in Electronic and Embedded Systems), EA 4353, Graduate School of Engineering ESIGELEC, Technopole du Madrillet, Avenue Galilée, BP 10024, 76801 Saint Etienne du Rouvray Cedex, France

^a e-mail: blaise.ravelo@yahoo.fr

Received: 20 September 2011
Revised: 26 December 2011
Accepted: 6 January 2012
Published online: 15 February 2012

Abstract

A relevant modeling-method of distributed interconnect line for the high-speed signal integrity (SI) application is introduced in this paper. By using the microwave and transmission line (TL) theory, the interconnect lines are assumed as its distributed RLC-model. Then, based on the transfer matrix analysis, the second-order global transfer function of the interconnect network comprised of the TL driven by voltage source including its internal resistance and the impedance load is expressed. Thus, mathematical analysis enabling the physical SI-parameters’ extraction was established by using the transient response of the loaded line. To verify the relevance of the developed model, RC- and RLC-lines excited by square-wavepulse with 10-Gbits/s-rate were investigated. So, comparisons with SPICE-computations were performed. As results, transient responses perfectly well correlated to the reference SPICE-models were evidenced. As application of the introduced model, evaluations of rise-/fall-times, propagation delays, signal attenuations and even the settling times were realized for different values of TL-parameters. Compared to other methods, the computation execution time and data memory consumed by the program implementing the proposed delay modeling-method algorithm are much better.