Issue 
Eur. Phys. J. Appl. Phys.
Volume 81, Number 3, March 2018



Article Number  30201  
Number of page(s)  10  
Section  Physics of Organic Materials and Devices  
DOI  https://doi.org/10.1051/epjap/2018180029  
Published online  08 June 2018 
https://doi.org/10.1051/epjap/2018180029
Regular Article
Experimental investigation on On–Off current ratio behavior near onset voltage for a pentacene based organic thin film transistor
^{1}
EPSMS, FST Errachidia, Université Moulay Ismail ( UMI ),
B.P. 509, Boutalamine,
Errachidia, Morocco
^{2}
XLIM UMR 7252  Université de Limoges/CNRS,
123 avenue Albert Thomas 
87060
Limoges Cedex, France
^{*} email: a.elamrani@fste.umi.ac.ma
Received:
16
January
2018
Received in final form:
11
March
2018
Accepted:
28
March
2018
Published online: 8 June 2018
The performance of a pentacene based organic thin film transistor (OTFT) with polymethylmethacrylate as a dielectric insulator and indium tin oxide based electrical gate is investigated. On the one hand, we showed that the threshold voltage increases with gate voltage, and on the other hand that it decreases with drain voltage. Thus, we noticed that the onset voltage shifts toward positive voltage values with the drain voltage increase. In addition, thresholdonset differential voltage (TODV) is proposed as an original approach to estimate an averaged carrier density in pentacene. Indeed, a value of about 4.5 × 10^{16} cm^{−3} is reached at relatively high gate voltage of −50 V; this value is in good agreement with that reported in literature with other technique measurements. However, at a low applied gate voltage, the averaged pentacene carrier density remains two orders of magnitude lower; it is of about 2.8 × 10^{14} cm^{−3} and remains similar to that obtained from space charge limited current approach for low applied bias voltage of about 2.2 × 10^{14} cm^{−3}. Furthermore, high I_{On}/I_{Off} and I_{On}/I_{Onset} current ratios of 5 × 10^{6} and 7.5 × 10^{7} are reported for lower drain voltage, respectively. The investigated OTFTs also showed good electrical performance including carrier mobility increasing with gate voltage; mobility values of 4.5 × 10^{−2} cm^{2} V^{−1} s^{−1} and of 4.25 × 10^{−2} cm^{2} V^{−1} s^{−1} are reached for linear and saturation regimes, respectively. These results remain enough interesting since current modulation ratio exceeds a value of 10^{7} that is a quite important requirement than high mobility for some particular logic gate applications.
© EDP Sciences, 2018
1 Introduction
During the last years, the improvement of organic materials and of implementation techniques makes possible to consider the organic thin film transistors (OTFTs) in various fields of application such as electronic circuits, digital circuits and displays [1–11]. In addition, among the most cited materials having interesting transport properties are oligothiophenes, phthalocyanines and polyacenes [12,13]; the mobilities are higher than 1 cm^{2} V^{−1} s^{−1}. Pentacene (Pn) is a conjugated molecule whose the assembly mode in the solid state leads to high ordered materials up to single crystal [14]. Thus, the most widely used polymers as gate dielectrics are polyvinylphenol (PVP), polymethylmethacrylate (PMMA), benzocyclobutene (BCB) and polyvinylalcohol (PVA) [15–18]. For these polymers calibration processes as a function of deposition rate must be investigated in order to obtain the required thickness [19–21]. In the case of a ptype semiconductor, the transistor operates in accumulation, which is the main mode of organic transistor operation [22]. Furthermore, several research works have been reported on the realization of an organic transistor with pentacene as ptype semiconductor [23–25]. Moreover, to understand the transport in an organic transistor channel, several parameters such as threshold voltage, field effect mobility, turn on voltage and others have been reported in literature [16,26–32].
Besides, the threshold voltage (V_{Th}) remains an interesting characteristic of transistors; V_{Th} is the minimum gate to source differential voltage that is needed to create a conducting channel between the source and drain electrodes [22,28,29]. V_{Th} can be calculated from the flat band voltage (V_{FB}) corresponding to the applied voltage required to establish a flat band regime for a metalsemiconductor contact energy diagram based on thin film transistor [22,31,33–35]. For the OTFTs, in particular, without doping, V_{FB} corresponds to the onset voltage V_{Onset} defined as the gate voltage associated with minimum drain current in the transfer characteristics of the transistor, where the charge carriers are accumulated at the interface and a channel current can flow [30]. For a p type semiconductor based OTFT, a positive turnon voltage can often be noticed, it is due to the fact that the device works in depletion regime [36]. Furthermore, an I_{On}/I_{Off} current modulation remains an interesting parameter for OTFTs that depends mainly on the mobility, charge density, conductivity and thickness of the semiconductor [37]. The depletion mode current I_{Off} is defined as the case of relatively no current flowing between the source and drain electrodes at a given V_{ds} voltage, while the accumulation mode current I_{On} corresponds to the substantial I_{ds} current flows for the given V_{ds} voltage [38]. Moreover, for logic gates, the I_{On}/I_{Off} ratio remains an important parameter that must be considered [39]. Thus, a high current modulation ratio exceeding 10^{8} is a quite important requirement than the high mobility for programmable electronic circuits [9,11,40,41].
In this present work, the performance of a pentacene based OTFTs is mainly investigated in forward sweep (Off to On), in terms of mobility, threshold voltage as well as onset voltage and on–off modulation current ratio. Thus, thresholdonset differential voltage (TODV) is investigated as a new practical approach to estimate the carrier density in an undoped pentacene based OTFT device.
2 Experimental details
As shown in Figure 1, a pentacenebased transistor with 1 μm thick PMMA as gate insulator was realized in topcontact geometry from a glass substrate (12 mm × 12 mm) covered with ITO (indiumtin oxide) thin film deposited by ion beam sputtering [42,43]. A PMMA thickness of 1 μm was deposited by spincoating onto the ITO electrode (150 nm) as the dielectric layers annealed at 165 °C during 1 h, followed by the deposition of a pentacene film of 50 nm [44]. The drain and source electrodes were made up of a thin gold film of about 50 nm by thermal vacuum evaporation (10^{−6} mbar) through a mask with a deposition rate of about 1 Å/s. The channel length is 100 μm with a width of 4 mm. These electrodes of gold (Au) present a high work function allowing good hole injection at the pentacene HOMO band [45]. The PMMA (from MicroChem ref. 950 with a chlorobenzene concentration of 7%) is deposited by the spincoating technique. The PMMA was chosen due to its resistivity that is higher than 2 × 10^{15} Ω cm and a roughness of about 0.3 nm. The dielectric constant is ε = 2.6 at 1 MHz and ε = 3.9 at 60 Hz, which is similar to reported values in the literature [46–48]. The capacity of the dielectric layer was recorded with a RLC impedance analyzer (HP 4284A) between 20 Hz and 1 MHz. The electrical characteristics of the investigated transistor were carried out using 4200 SMU Keithley equipment controlled by computer. All the devices were tested at room temperature and in open air.
Fig. 1
Schematic cross section of the pentacene based organic thin film transistor. 
3 Results and discussion
As shown in Figure 2, from the electrical characteristics of the pentacenebased pchannel TFTs, two main regimes are noticed. As illustrated in Figure 2a, a linear regime given by equation (1) is given for 0 < V_{ds} ≪ V_{gs}−V_{Th}_{,} where I_{ds} can be related to drain voltage and gate voltage by the following formula [49]: (1) (2)
The saturation regime (Eq. (2)) is reached when V_{ds} > V_{gs}−V_{Th} > 0; the current I_{ds} independent of source–drain voltage. The other zone called subthreshold regime (Eq. (3)) is also provided for V_{gs} between V_{Th} and V_{Onset} (0 < V_{Th} < V_{gs} < V_{Onset}) (Fig. 2c), in which the current takes an exponential dependence on V_{gs}, and it can be expressed as follow [50–52]: (3) where I_{0} is the drain current obtained when V_{gs} ≈ V_{Onset}, k is the Boltzman constant, n is the ideality factor and T is the temperature. These behaviors of electrical characteristics remain in good agreement with that reported in literature [22,49,50].
The hysteresis and transfer characteristics of transistors in forward sweep (Off to On) V_{gs} and backward sweep (On to Off) were slightly investigated. As shown in Figure 2e, the transfer characteristics in forward and backward sweeps remain identical in accumulation regime (i.e. for enough higher V_{gs}). However, a hysteresis phenomenon was noticed at low applied gate voltage (i.e. Off mode); the Off current passes from 1.5 × 10^{−12}A to about 10^{−11}A at V_{gs} = 0 V. This behavior can be due either to injected charges from the gate electrode that then trapped in the dielectric bulk, or to trapped electrons at the dielectric/semiconductor interface [53]. Furthermore, for transistors with Pn/PMMA interface, the hysteresis effect remains negligible and can be avoided for optimized structures [54]. Thus, it was reported that the hysteresis may depends on different parameters such as ambient air, vacuum, dielectric thickness and sweep test, and can be avoided in some conditions [55]. However, this behavior may be manipulated and explored in organic transistor toward memory elements [56]. As mentioned above, our study is only investigated in forward sweep (Off to On). This hysteresis behavior needs a study with further details, which may be the subject of our future work.
V_{Th} is generally given by the intercept of the linear part slope of (I_{ds})^{1/2} versus V_{gs} transfer characteristic plot with the abscissa (Fig. 2d). Thus, the onset voltage V_{Onset} corresponds to the gatesource voltage at which the drain current reaches a minimum, and is obtained from the log (I_{ds}) versus V_{gs} transfer characteristic curve [57,58]. As shown in Figure 3a, V_{Th} decreases with the drain voltage increase. However, it increases linearly with the maximum applied gate voltage. As mentioned above, the threshold voltage corresponds to the gate voltage that allowing the channel begins to form between the source and drain electrodes [22,28], which is expressed by equation (4) as follows [22,31,33,34,59–61]: (4) with V_{FB} is the flat band voltage that can be given by the equation (5) as [62]: (5)where C_{i} is the capacity of the insulator per unit area. p_{0} is the free carrier density at equilibrium and d_{s} is the thickness of the semiconductor. Thus, W_{M} and W_{S} are the gate and semiconductor work functions, respectively. q is the elementary charge, and Q_{is} is the interface charge density. In equation (4), the parameter corresponds to the presence of thermal charges in the volume of the film. The effect of this parameter on V_{Th} remains low for an organic semiconductor with a low carrier density. V_{FB} is due to the difference between W_{M} and W_{S}, and to the presence of interface charge density Q_{is} [63]. Moreover, the threshold voltage can be associated with the charges trapped in interface states and the injection barrier at the source electrode [35]. It can be related to the surface charge density σ_{s} of OHgroups at the pentacene/insulator interface and the thickness of the insulator [29]. Thus, in the case of pentacene based TFT transistor, it was reported also that V_{Th} can be expressed by the following formula (Eq. (6)) [32]: (6)where Φ_{S} is the surface potential, ε_{0} is the vacuum permittivity, ε_{s} is the permittivity of pentacene, q is the electron charge, and N_{ts} is the trap density. However, the equation (6) was initially investigated for nanocrystalline silicon based thinfilm transistor operating under an inversion regime [64].
In addition, for OTFTs in particular without doping or for the low doping level of the semiconductor, V_{FB} corresponds to the onset voltage V_{Onset} which is defined as the gate voltage corresponding to the minimum drain current in the transfer characteristics of the transistor, where charge carriers are accumulated at the interface and a channel current can flow [30]. Thus, the onset voltage V_{Onset} defined as the gatesource voltage at which the drain current reaches a minimum value, and is obtained from the log (I_{dS}) versus V_{gs} transfer characteristic curves (Fig. 2c) [57,58]. In the case of a doped semiconductor, V_{Onset} can be defined by the equation (7) as follows [58,60,65]: (7) where N_{A} is the doping concentration. In the case of an undoped semiconductor or enough low doping level of the semiconductor, V_{Onset} can be considered as the flat band voltage V_{FB}. As shown in Figure 3b, the threshold voltage increases linearly with the gate voltage, which is due to the induced carrier number increase as we will see further. Figure 3c illustrates the onset voltage versus drain voltage; it remains unchanged for a lower drain voltage, while for a high drain voltage, it decreases more remarkably and shifts towards lower and positive values; the onset voltage passes from about −9 V at V_{ds} = −5 V to −3 V at V_{ds} = −40 V. It was recently reported that the field effect mobility in an organic semiconductor based TFT device is affected by both gate and drain voltages. Moreover, it was noticed that the sourcedrain voltage has a stronger effect on the channel electric field than the gatesource voltage for most cases [66].
From the two different previous equations (4) and (7), the approximate free carrier density can be estimated in the case of an undoped semiconductor or for a lower doping concentration from the following expression (Eq. (8)): (8)
Thus, we can estimate the averaged carrier density with this proposed thresholdonset differential voltage (TODV) approach. As shown in Figure 4, the carrier density increases with the gate voltage; the carriers density reaches a value of about 4.3 × 10^{16} cm^{−3} for V_{gs} = −50 V and V_{ds} = −40 V. In other works, the hole concentration in the accumulation region of the organic/dielectric interface is of about 1.7 × 10^{16} cm^{−3} by using the capacitance–voltage (C–V) and deeplevel transient spectroscopy (DLTS) measurements for a metal/insulator/pentacene based structure device [67]. For low applied gate voltage (i.e. V_{gs} ≈ −10 V), we obtain an averaged carrier density of about 2.8 × 10^{14} cm^{−3}, which is two orders of magnitude lower; it is similar to that obtained for a pentacene bulk carrier density obtained with SCLC (space charge limited current) method [68]. Indeed, Figure 4c shows the current density characteristic versus voltage in logarithmic scale plot that allows distinguishing different regions with bias voltage (region I, region II, region III and region IV). Thus, the number of carriers p_{0} can be extracted from the equation (9) given as follows [68]: (9) where V_{Ω} is the ohmic voltage. The carrier density p_{0} is estimated from J (V) characteristics for a bulk pentacene thickness of 150 nm in a sandwich structure (ITO(150 nm)/Pn(150 nm)/Al) and with a permittivity of pentacene film ε_{s} = 4, and V_{Ω} = 2 × 10^{−2} V. Indeed, the obtained carrier density thermally generated at a low voltage is about 2.2 × 10^{14} cm^{−3}. These reported values are coherent to those obtained for a theoretical simulation result of a pentacene transistor in other work [69]. In addition, it was reported also that the injection barrier can affect the threshold voltage and hole concentration across the channel due to the strong tendency to form a nonOhmic contact at metal/organic junctions [70].
The I_{On}/I_{Off} current modulation is the ratio of the current in the accumulation mode over the current in the depletion mode. The I_{Off} is defined as the case of little or no current flowing between the source and drain electrodes at a given sourcedrain voltage, while the I_{On} refers to the substantial sourcedrain current flows for the given source drain voltage [38]. For many memory and display applications, a high I_{On}/I_{Off} ratio exceeding 10^{8} is a more important requirement than a high mobility [40]. The I_{On}/I_{Off} ratio can be defined as follows [41,63,71,72]: (10) where the off state current I_{Off} (i.e. leakage current) can be calculated at V_{gs} = 0 V; it can vary linearly with drain voltage as [41]: (11)
The onstate current I_{On} is considered for V_{gs} different from 0 V and higher than the threshold voltage, and for constant V_{ds}. Thus, the current ratio may depend on the working mode of the device as well as on the drain voltage [73]. Indeed, for onstate current mode I_{On} corresponding to linear regime (Eq. (1)) and saturation regime (Eq. (2)), the current ratio can be expressed by equations (12) and (13) as: (12) and (13)
For the particular voltage V_{ds} = V_{gs} − V_{Th}, and from equations (12) and (13), the current ratio can be expressed by the following formula of equation (14) as: (14) where μ_{FE} is the field effect mobility for the particular voltage (i.e. V_{ds} = V_{gs} − V_{Th}).
In addition, Table 1 shows the main different expressions for I_{On}/I_{Off} that have been reported in literature. We noticed for the most of these formulas that mobility over conductivity ratio () is the main parameter that affects the I_{On}/I_{Off} values. Thus, it was reported that a high I_{On}/I_{Off} ratio remains possible for low doping level, thinner pentacene films, and high capacity of the dielectric insulators (i.e. low dielectric thickness) [22,28,37,38,41,60]. Figure 5a shows the off state current versus drain voltage without gate voltage; the current increases linearly with drain voltage. Figures 5b and 5c show the I_{On}/I_{Off} versus drain voltage and gate voltage for different maximum gate and drain voltages, respectively. The I_{On}/I_{Off} decreases with V_{ds} whereas it increases with V_{dg}. We noticed a high I_{On}/I_{Off} ratio of about 5 × 10^{6} for a maximum gate voltage V_{gs} = −50 V and a lower drain voltage V_{ds} = −TV. At a low drain voltage (i.e. linear regime), the effect of gate voltage on I_{On}/I_{Off} ratio remains more emphasized (Eq. (12)), while for a high drain voltage (i.e. accumulation regime), this ratio notably decreases; this behavior is in agreement with the equation (13), and it may be also due to conductivity increase with drain voltage [74].
Equations (12)–(14) are considered for the linear evolution behavior of the offstate (I_{Off}) current versus drain voltage (Eq. (11)). However, other leakage sources of current can exist such as gate current leakage and noise that can make the behavior nonlinear. Indeed, the I_{On}/I_{Off} ratio becomes more difficult to establish [75]. To generalize the result, a nonlinear dependence of I_{Off} with drain voltage must be considered. Thus, the mobility generally increases with the gate voltage as μ_{FE} = μ_{GVD} ≈ μ_{0} (V_{gs} − V_{Th}) ^{α} [28], where μ_{0} is known as the band mobility of the semiconductor under analysis, μ_{GVD} is the field dependent mobility, and α is the mobility enhancement factor. In addition, as mentioned above, the onset voltage V_{Onset} or switchon voltage V_{so} illustrates the gatesource voltage at which the drain current reaches a minimum [76]. When a gate voltage is applied around the onset voltage (i.e. V_{gs} ≈ V_{Onset}), the transistor may be considered in “off” mode; in this case, the drain current is of minimum value I_{dsmin} (i.e. I_{Onset}) at V_{Onset}. Thus, as shown in equation (15), we defined an I_{On}/I_{Onset} parameter as the ratio between maximum drain current I_{dsmax} and minimum drain current I_{Onset} as: (15)
Figure 6a shows the “off” state current and I_{On}/I_{Onset} versus drain voltage for an onset applied gate voltage and a gate voltage for different maximum gates, respectively. Thus the onset current does not increase linearly with drain voltage as shown previously; an exponential fit is more appropriate for the evolution of I_{Onset} versus drain voltage (Fig. 6a); the exponential fit was obtained with the correlation factor R = 0.995, which the formula of I_{Onset} can be given by equation (16) as follows: (16) where I_{V}_{ds0} is the drain current at a very low drain voltage that can be a function of conductivity, thickness of the semiconductor as well as technology parameters (L and W), and b is a constant; in our case I_{V}_{ds0} = 5 × 10^{−14} A and b = 0.162.
Figure 6b illustrates the I_{On}/I_{Onset} ratio versus drain voltage for different gate voltages. Thus, a high I_{On}/I_{Off} current ratio of about 7.5 × 10^{7} is obtained for V_{gs} = −50 V and V_{ds} = −10 V. Figure 6c illustrates the I_{On}/I_{Onset} versus gate voltage for different drain voltages. From this figure, a similar behavior is noticed to that presented in Figure 5c concerning the evolution of I_{On}/I_{Off} versus gate voltage. Thus, the current ratio can be given by the equations (17) and (18) corresponding to the linear regime and saturation regime, respectively, as follows: (17) and (18)
For the particular voltage V_{ds} = V_{gs} − V_{Th}, the current ratio can be expressed by the equation (19) as: (19)
In the subthreshold region, the drain current is due to carriers that have sufficient thermal energy to overcome the gatevoltagecontrolled energy barrier near the source contact and mainly diffuse, rather than drift, through the semiconductor to the drain contact [76]. The inverse subthreshold slope S that is expressed in volt per decade (V/dec.) can be analyzed by using the following equation [27,51,78]: (20) where n is the ideality factor. The parameter S corresponds to the gate voltage needed to increase the drain current of a decade, which also reflects the quality of insulator/semiconductor interface [79]. A higher trap density can result in a gentle slope, which leads to poor modulation switching behavior [65]. Moreover, the maximum number of interface traps can be estimated using the following formula (Eq. (21)) considering that the densities of deep bulk as well as interface states remain independent of energy [27,79,80]: (21)
As shown in Figure 7, the maximum number of interface traps and the inverse subthreshold slope S parameter increase with drain voltage. As reported by Ralland [79], a high number of interface traps can leads to a high value of S and consequently poor switching behavior of the device.
The field effect mobilities in the linear regime and in the saturation regime can be extracted for V_{gs}>V_{Th} from the equations (1) and (2) as expressed as follows (Eqs. (22) and (23)): (22) (23)
Figure 8 shows the field effect mobilities in the two regime (linear and saturation) that remain of the same order of magnitude for the both regimes. Figure 8a shows that the field effect mobility of the pentacene based OTFT device extracted for V_{gs}>V_{Th} in the linear regime (i.e. V_{ds} = −5 V); the mobility increases until a maximum value then it saturates with increasing V_{gs}. Thus, the mobility reaches a maximum value of about 4.5 × 10^{−2} cm^{2} V^{−1} s^{−1} for V_{gsmax} = −45 V. Figure 8b shows that the field effect mobility extracted for for V_{gs}>V_{Th} in saturation regime of the pentacene based OTFT device increases slightly with increasing V_{ds}, but the mobility increases until a maximum value (of about 4.25 × 10^{−2} cm^{2} V^{−1} s^{−1}) and then it decreases with increasing V_{gs} for a given drain voltage. A similar behavior was reported in other works [81,82]; the saturation is due to the contact resistance effect at drain and source interfaces [22,83]. It was also reported that the potential barrier at grain boundaries of polycrystalline organic semiconductors decreases with gate voltage, which increases the mobility [82]. Moreover, the slight increase in mobility with drain voltage may be due to the carrier transit time which is inversely proportional to the drain voltage [84,85]; higher drain voltage may involve lower time transit and consequently higher mobility [73]. Thus, generally the total resistance of the transistor decreases with the applied gate voltage [86,87]. However, nonnegligible contact resistance for pentacene/Aubased transistor was reported [88]. Moreover, the influence of contact resistance becomes more significant in short channel transistors for high frequency applications [89]. Thus, the contact resistance effect is often more pronounced for transistor devices with bottom electrodes (source and drain) contacts. Indeed, to account the contact resistance effect, a voltage drop can be mainly noticed for the voltage V_{ds} [90].
Fig. 2
Electrical characteristics of pentacenebased TFT: (a) I_{ds} I_{ds} − V_{ds} output characteristics; (b) I_{ds} − V_{gs} transfer characteristics for different gate voltages; (c) log (−I_{ds}) versus V_{gs} curves for different drain voltages; (d) transfer characteristics for different drain voltages; (e) log (−I_{ds}) versus V_{gs} plot in forward and backward sweeps. 
Fig. 3
(a) Plots of threshold voltage versus drain voltage for different gate voltages. (b) Plots of threshold voltage versus gate voltage for different drain voltages. (c) Onset voltage and on state drain voltage versus drain voltage for pentacene based thin film transistor. 
Fig. 4
(a) Carrier density versus drain voltage for different gate voltages. (b) Carrier density versus gate voltage for different drain voltages. (c) Logarithmic scale plot of current density of ITO (150 nm)/Pn ((150 nm)/Al structure versus bias voltage [68]. 
Summary of the most common formulas used in literature for ratio parameter.
Fig. 5
(a) I_{Off} versus drain voltage without gate voltage. (b) I_{On}/I_{Off} ratio versus drain voltage for different gate voltages. (c) I_{On}/I_{Off} ratio versus maximum gate voltage for different drain voltages. 
Fig. 6
(a) I_{Onset} versus drain voltage for an applied gate voltage at an onset voltage. (b) I_{On}/I_{Onset} ratio versus drain voltage for different gate voltages. (c) I_{On}/I_{Onset} ratio versus a maximum gate voltage for different drain voltages. 
Fig. 7
Maximum number of interface traps and S parameter versus drain voltage for given gate voltage V_{gs} = −50 V and V_{ds} = −30 V. 
Fig. 8
Field effect mobility versus maximum applied gate voltage V_{gsmax} (a) in the linear regime (V_{ds} = −5 V). (b) in the saturation regime for different drain voltages V_{ds} (−20, −30 and −40 V). 
4 Conclusion
In this present work, a pentacene based organic thin film transistor with PMMA as a dielectric insulator and ITO based electrical gate was studied. We noticed an increase in the threshold voltage with an applied gate voltage, which decreases with drain voltage increase. Thus, we reported that the onset voltage shifts toward positive voltage values by increasing the drain voltage. Furthermore, the ThresholdOnset Differential Voltage (TODV) was investigated as a new approach to estimate the carrier density in pentacene. Indeed, a value of about 4.5 × 10^{16} cm^{−3} was reported at relatively high gate voltage of −50 V which remains in good agreement with literature. However, at a low applied gate voltage, the pentacene carrier density is two orders of magnitude lower (2.8 × 10^{14} cm^{−3}) and remains similar to that obtained from space charge limited current approach for a low applied bias voltage (2.2 × 10^{14} cm^{−3}). The high I_{On}/I_{Off} and I_{On}/I_{Onset} current ratios of 5 × 10^{6} and 7.5 × 10^{7} were noticed for lower drain voltage, respectively. For the pentacene based OTFTs, we showed also the carrier mobility increase with applied maximum gate voltage; the mobility values of of 4.5 × 10^{−2} cm^{2} V^{−1}s^{−1} and of 4.25 × 10^{−2} cm^{2} V^{−1}s^{−1} are reached for linear and saturation regimes, respectively. The obtained results remain enough interesting since, for some flexible logic gates applications, a current modulation ratio exceeding a value of 10^{7} is a quite important requirement than the high mobility.
Nomenclature
HOMO: highest occupied molecular orbital
LUMO: lowest unoccupied molecular orbital
OFET: organic field effect transistor
OTFT: organic thin film transistor
d_{s}: thickness of the semiconductor
h: height of the semiconducting layer
d_{i}: thickness of the insulator
N_{A}: acceptor dopants concentration
Q_{is}: interface states density
: maximum number of interface states
μ_{r}: mobility of residual charge
ρ_{r}: density of residual charge
p_{0}: carriers charge density
μ_{GVD}: field dependent mobility
μ_{lin}: mobility in linear regime
μ_{sat}: mobility in saturation regime
V_{gsmax}: maximum applied gatesource voltage
I_{dsmin}: minimum of drain current
I_{Off}: drain current in off state mode
I_{On}: drain current in on state mode
I_{Onset}: current at onset voltage
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Cite this article as: Aumeur El Amrani, Abdeljabbar Essaghiri, ElMahjoub Boufounas, Bruno Lucas, Experimental investigation on On–Off current ratio behavior near onset voltage for a pentacene based organic thin film transistor, Eur. Phys. J. Appl. Phys. 81, 30201 (2018)
All Tables
All Figures
Fig. 1
Schematic cross section of the pentacene based organic thin film transistor. 

In the text 
Fig. 2
Electrical characteristics of pentacenebased TFT: (a) I_{ds} I_{ds} − V_{ds} output characteristics; (b) I_{ds} − V_{gs} transfer characteristics for different gate voltages; (c) log (−I_{ds}) versus V_{gs} curves for different drain voltages; (d) transfer characteristics for different drain voltages; (e) log (−I_{ds}) versus V_{gs} plot in forward and backward sweeps. 

In the text 
Fig. 3
(a) Plots of threshold voltage versus drain voltage for different gate voltages. (b) Plots of threshold voltage versus gate voltage for different drain voltages. (c) Onset voltage and on state drain voltage versus drain voltage for pentacene based thin film transistor. 

In the text 
Fig. 4
(a) Carrier density versus drain voltage for different gate voltages. (b) Carrier density versus gate voltage for different drain voltages. (c) Logarithmic scale plot of current density of ITO (150 nm)/Pn ((150 nm)/Al structure versus bias voltage [68]. 

In the text 
Fig. 5
(a) I_{Off} versus drain voltage without gate voltage. (b) I_{On}/I_{Off} ratio versus drain voltage for different gate voltages. (c) I_{On}/I_{Off} ratio versus maximum gate voltage for different drain voltages. 

In the text 
Fig. 6
(a) I_{Onset} versus drain voltage for an applied gate voltage at an onset voltage. (b) I_{On}/I_{Onset} ratio versus drain voltage for different gate voltages. (c) I_{On}/I_{Onset} ratio versus a maximum gate voltage for different drain voltages. 

In the text 
Fig. 7
Maximum number of interface traps and S parameter versus drain voltage for given gate voltage V_{gs} = −50 V and V_{ds} = −30 V. 

In the text 
Fig. 8
Field effect mobility versus maximum applied gate voltage V_{gsmax} (a) in the linear regime (V_{ds} = −5 V). (b) in the saturation regime for different drain voltages V_{ds} (−20, −30 and −40 V). 

In the text 
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